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Instruction set architecture
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61	MIPS Assembly Language Programmer’s Guide ASM-01-DOC Your comments on our products and publications Add to Reading List Source URL: www.tik.ee.ethz.ch Language: English - Date: 2009-09-02 12:08:50 Computer architecture Computing Computer engineering Central processing unit Instruction set architectures Assembly languages Programming language implementation Reduced instruction set computing IBM Basic assembly language and successors Processor register Instruction set Coprocessor
62	Document: ! ! ! Add to Reading List Source URL: www.stanq.com Language: English - Date: 2015-08-26 16:18:18 Computer architecture Computing Digital Equipment Corporation Instruction set architectures Advanced RISC Computing Charon Information technology AlphaServer Tru64 UNIX DEC Alpha OpenVMS 64-bit computing
63	Secure AES Implementation on a 32-bit RISC-V Processor Advisor(s): Hannes Groß Institute for Applied Information Processing and Communications (IAIK) Graz University of Technology, Austria Add to Reading List Source URL: www.iaik.tugraz.at Language: English - Date: 2016-02-24 05:00:01 Instruction set architectures Reduced instruction set computing RISC-V Instruction set ARM architecture Comparison of instruction set architectures
64	Analysis of Cross-layer Vulnerability to Variations: An Adaptive Instruction-level to Task-level Approach 1 Abbas Rahimi CSE, UC San Diego La Jolla, CA 92093, USA Add to Reading List Source URL: mesl.ucsd.edu Language: English - Date: 2014-02-11 01:12:49 Parallel computing Central processing unit Computer architecture Instruction set architectures Instruction set SIMD Program counter ARM architecture Processor register General-purpose computing on graphics processing units OpenMP
65	CS:APP2e Guide to Y86 Processor Simulators∗ Write back Stat Add to Reading List Source URL: csapp.cs.cmu.edu Language: English - Date: 2013-07-29 12:14:16 Simulation software Central processing unit Computer architecture Assembly language Programming language implementation Instruction set simulator Register file Instruction set Pointer GNU Core Utilities
66	Intel’s Expands Product Portfolio for Networking, Storage and Internet of Things Nov. 9, 2015 — Faced with the rising tide of data-heavy digital services and billions of connected devices, communications networks are Add to Reading List Source URL: download.intel.com Language: English - Date: 2015-11-06 16:37:27 X86 architecture Instruction set architectures Xeon Data Plane Development Kit Hyper-threading Intel Core Intel X86 virtualization X86 Mac Pro ThinkServer
67	Godson-2E software manual Contents 1 Godson-2E Micro Architecture...................................................................................1 1.1 Godson Series Processors ........................................ Add to Reading List Source URL: dev.lemote.com Language: English - Date: 2011-05-04 12:04:52 Central processing unit CPU cache Translation lookaside buffer Loongson Processor register Control register Instruction set Addressing mode MIPS instruction set Draft:Cache memory
68	Using Cortex-M3 and Cortex-M4 Fault Exception Application Note 209 Abstract The Cortex-M processors implement an efficient exception model that also traps illegal memory accesses and several incorrect program conditions. Add to Reading List Source URL: www.keil.com Language: English - Date: 2016-03-11 03:37:29 Computer errors Memory management Central processing unit Instruction set architectures ARM architecture Bus error Control register Page fault Segmentation fault Memory protection ARM Cortex-M Exception handling
69	MAKING IoT POSSIBLE expresslogic Add to Reading List Source URL: rtos.com Language: English - Date: 2016-05-23 14:49:51 Instruction set architectures Microcontrollers Real-time operating systems Embedded microprocessors ThreadX Blackfin Embedded software USB Embedded system ARM architecture AVR32 ARC
70	Under 100-cycle Thread Migration Latency in a Single-ISA Heterogeneous Multi-core Processor Elliott Forbes, Zhenqian Zhang, Randy Widialaksono, Brandon Dwiel, Rangeen Basu Roy Chowdhury, Vinesh Srinivasan, Steve Lipa, Er Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2015-08-21 02:18:29 Central processing unit Microprocessors Computer architecture Parallel computing Instruction set architectures Multi-core processor ARM architecture Microarchitecture ARM Cortex-A15 AMD 10h ARM big.LITTLE Processor register

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